Digital video capabilities can be incorporated into a wide range of devices, including digital televisions, digital direct broadcast systems, wireless broadcast systems, personal digital assistants (PDAs), laptop or desktop computers, digital cameras, digital recording devices, digital media players, video gaming devices, video game consoles, cellular or satellite radio telephones, video teleconferencing devices, and the like. Some applications may involve sending video data to multiple display panels in a tiled arrangement to display a single video output across multiple displays.
One key challenge is to present a unified and synchronized display across all panels. Because of difference in oscillator due to temperature and voltage variances, the same programming on the same type of display hardware will have different refresh rate and different VSYNC timing and may result in undesirable visual artifacts. For example, if there is 500 part per million difference (500 PPM) which is about 0.5 millisecond error for every 1 second (˜43 seconds per day). In case of 60 Hz refresh rate (e.g., 16.6 milliseconds for every cycle), it takes about 33 sec to deviate by almost 1 video frame for the 500 PPM difference. Most of the display programming is double buffered to avoid tearing, and the setup of the display submission to the display hardware will have the effect on the next frame starting from VSYNC. Different VSYNC timing results in different time display update on different panels, and in turn, results in visual artifact across an array of panels.
One possible solution is to make all panels have common refresh timing, often referred to as “genlock.” Issuing a common buffer swap is typically accomplished by swap barrier in flipping graphical content as soon as all the renderings are finished or by timestamp in displaying video in a constant movie playback rate (for example, 24 fps). Common refresh timing (e.g., genlock) is usually handled with hardware that is configured to implement refresh timing using a master synchronization signal.
One possible genlock synchronization may involve a single graphics/display controller with an adaptor for each display panels. Although this solution may allow each display interface be configured in the same graphic card to produce the same display refresh property to different panels for the genlock synchronization, it may not be easy to make this solution scalable to more than the adaptor's limit on the specific card, such as potentially to support up to six display panels, but no more. Limited GPU capability and memory size restriction may occur in a single graphics card.
Another possible solution may involve multiple display controllers using dedicated hardware for a master genlock signal to drive multiple displays. Although this solution may take advantage of distributing parallel processing power and graphics processing unit (GPU) capability and memory may not be a problem, this solution requires additional software swap (flip) synchronization mechanism such as a swap barrier. This solution may involve requiring hardware enhancement to provide a frame genlock master signal for display timing to each display device mainly in PC. It may be complicated and expensive to add additional displays because of the hardware requirement of feeding the sync signal from the master to every “special” display controller in the group.
Another possible solution may involve using a cable to wire a parallel port of a PC to an external signal generator to keep synchronization. Although this solution may take advantage of distributing parallel processing power, and GPU scalability, memory, and special hardware card may not be a problem, this solution still needs to hardwire a cable between a parallel port's interrupt line and the external signal generator for display timing. This solution may be difficult to scale an array of panels because of additional hardwired connection requirements, and current display panel design may not have any parallel port or exposed interrupt line.
Techniques of the present disclosure may address the genlock issue discussed above using a process without the hardwired synchronization signal and may be simpler and less expensive.